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EN29LV320A EN29LV320A 32 Megabit (4096K x 8-bit / 2048K x 16-bit) Flash Memory Boot Sector Flash Memory, CMOS 3.0 Volt-only
FEATURES
* Single power supply operation - Full voltage range: 2.7 to 3.6 volts read and write operations * High performance - Access times as fast as 70 ns * Low power consumption (typical values at 5 MHz) - 9 mA typical active read current - 20 mA typical program/erase current
- Less than 1 A current in standby or automatic sleep mode.
* Standard DATA# polling and toggle bits feature * Unlock Bypass Program command supported * Erase Suspend / Resume modes: Read and program another Sector during Erase Suspend Mode * Support JEDEC Common Flash Interface (CFI). * Low Vcc write inhibit < 2.5V * Minimum 100K program/erase endurance cycles. * RESET# hardware reset pin - Hardware method to reset the device to read mode. * WP#/ACC input pin - Write Protect (WP#) function allows protection of outermost two boot sectors, regardless of sector protect status - Acceleration (ACC) function provides accelerated program times * Package Options - 48-pin TSOP (Type 1) - 48 ball 6mm x 8mm FBGA * Commercial and Industrial Temperature Range.
* Flexible Sector Architecture: - Eight 8-Kbyte sectors, sixty-three 64k-byte sectors. - 8-Kbyte sectors for Top or Bottom boot. - Sector/Sector Group protection: Hardware locking of sectors to prevent program or erase operations within individual sectors Additionally, temporary Sector Group Unprotect allows code changes in previously locked sectors. * High performance program/erase speed Word program time: 8s typical Sector erase time: 500ms typical Chip erase time: 70s typical
* JEDEC Standard compatible
GENERAL DESCRIPTION
The EN29LV320A is a 32-Megabit, electrically erasable, read/write non-volatile flash memory, organized as 4,194,304 bytes or 2.097,152 words. Any word can be programmed typically in 8s. The EN29LV320A features 3.0V voltage read and write operation, with access times as fast as 70ns to eliminate the need for WAIT states in high-performance microprocessor systems. The EN29LV320A has separate Output Enable (OE#), Chip Enable (CE#), and Write Enable (WE#) controls, which eliminate bus contention issues. This device is designed to allow either single Sector or full Chip erase operation, where each Sector can be individually protected against program/erase operations or temporarily unprotected to erase or program. The device can sustain a minimum of 100K program/erase cycles on each Sector.
.
This Data Sheet may be revised by subsequent versions 1 or modifications due to changes in technical specifications.
(c)2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2007/07/17
EN29LV320A
CONNECTION DIAGRAMS
FBGA Top View, Balls Facing Down
A6 B6 C6 D6 E6 F6 G6 H6
A13
A12
A14
A15
A16
BYTE#
DQ15/A-1
Vss
A5
B5
C5
D5
E5
F5
G5
H5
A9
A8
A10
A11
DQ7
DQ14
DQ13
DQ6
A4
B4
C4
D4
E4
F4
G4
H4
WE#
RESET#
NC
A19
DQ5
DQ12
Vcc
DQ4
A3
B3
C3
D3
E3
F3
G3
H3
RY/BY# A2
WP# /ACC B2
A18 C2
A20 D2
DQ2 E2
DQ10 F2
DQ11 G2
DQ3 H2
A7 A1
A17 B1
A6 C1
A5 D1
DQ0 E1
DQ8 F1
DQ9 G1
DQ1 H1
A3
A4
A2
A1
A0
CE#
OE#
Vss
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
2 (c)2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2007/07/17
EN29LV320A
TABLE 1. PIN DESCRIPTION LOGIC DIAGRAM
Pin Name A0-A20 DQ0-DQ14 DQ15 / A-1 CE# OE# WE# WP#/ACC RESET# BYTE# RY/BY# Vcc Vss NC
Function 21 Address inputs 15 Data Inputs/Outputs DQ15 (data input/output, in word mode), A-1 (LSB address input, in byte mode) Chip Enable Output Enable Write Enable Write Protect / Acceleration Pin Hardware Reset Pin Byte/Word mode selection Ready/Busy Output Supply Voltage (2.7-3.6V) Ground Not Connected to anything
EN29 LV320
A0 - A20 WP#/ACC RESET# CE# OE# WE# BYTE# RY/BY#
DQ0 - DQ15 (A-1)
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
3 (c)2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2007/07/17
EN29LV320A
ORDERING INFORMATION
EN29LV320A
T
70
T
C
P PACKAGING CONTENT (Blank) = Conventional P = Pb Free
TEMPERATURE RANGE C = Commercial (0C to +70C) I = Industrial (-40C to +85C) PACKAGE T = 48-pin TSOP B = 48-Ball Fine Pitch Ball Grid Array (FBGA) 0.80mm pitch, 6mm x 8mm package SPEED 70 = 70ns 90 = 90ns
BOOT CODE SECTOR ARCHITECTURE T = Top boot Sector B = Bottom boot Sector
BASE PART NUMBER EN = EON Silicon Solution Inc. 29LV = FLASH, 3V Read, Program and Erase 320A = 32 Megabit (4M x 8 / 2M x 16)
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
4 (c)2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2007/07/17
EN29LV320A
Table 2A. Top Boot Sector Address Tables (EN29LV320AT)
U
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37
A20 - A12 000000xxx 000001xxx 000010xxx 000011xxx 000100xxx 000101xxx 000110xxx 000111xxx 001000xxx 001001xxx 001010xxx 001011xxx 001100xxx 001101xxx 001110xxx 001111xxx 010000xxx 010001xxx 010010xxx 010011xxx 010100xxx 010101xxx 010110xxx 010111xxx 011000xxx 011001xxx 011010xxx 011011xxx 011100xxx 011101xxx 011110xxx 011111xxx 100000xxx 100001xxx 100010xxx 100011xxx 100100xxx 100101xxx
Sector Size (Kbytes / Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32
Address Range (h) Byte mode (x8) 000000-00FFFF 010000-01FFFF 020000-02FFFF 030000-03FFFF 040000-04FFFF 050000-05FFFF 060000-06FFFF 070000-07FFFF 080000-08FFFF 090000-09FFFF 0A0000-0AFFFF 0B0000-0BFFFF 0C0000-0CFFFF 0D0000-0DFFFF 0E0000-0EFFFF 0F0000-0FFFFF 100000-10FFFF 110000-11FFFF 120000-12FFFF 130000-13FFFF 140000-14FFFF 150000-15FFFF 160000-16FFFF 170000-17FFFF 180000-18FFFF 190000-19FFFF 1A0000-1AFFFF 1B0000-1BFFFF 1C0000-1CFFFF 1D0000-1DFFFF 1E0000-1EFFFF 1F0000-1FFFFF 200000-20FFFF 210000-21FFFF 220000-22FFFF 230000-23FFFF 240000-24FFFF 250000-25FFFF
Address Range (h) Word Mode (x16) 000000-007FFF 008000-00FFFF 010000-017FFF 018000-01FFFF 020000-027FFF 028000-02FFFF 030000-037FFF 038000-03FFFF 040000-047FFF 048000-04FFFF 050000-057FFF 058000-05FFFF 060000-067FFF 068000-06FFFF 070000-077FFF 078000-07FFFF 080000-087FFF 088000-08FFFF 090000-097FFF 098000-09FFFF 0A0000-0A7FFF 0A8000-0AFFFF 0B0000-0B7FFF 0B8000-0BFFFF 0C0000-0C7FFF 0C8000-0CFFFF 0D0000-0D7FFF 0D8000-0DFFFF 0E0000-0E7FFF 0E8000-0EFFFF 0F0000-0F7FFF 0F8000-0FFFFF 100000-107FFF 108000-10FFFF 110000-117FFF 118000-11FFFF 120000-127FFF 128000-12FFFF
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
5 (c)2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2007/07/17
EN29LV320A
SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 100110xxx 100111xxx 101000xxx 101001xxx 101010xxx 101011xxx 101100xxx 101101xxx 101110xxx 101111xxx 110000xxx 110001xxx 110010xxx 110011xxx 110100xxx 110101xxx 110110xxx 110111xxx 111000xxx 111001xxx 111010xxx 111011xxx 111100xxx 111101xxx 111110xxx 111111000 111111001 111111010 111111011 111111100 111111101 111111110 111111111 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 260000-26FFFF 270000-27FFFF 280000-28FFFF 290000-29FFFF 2A0000-2AFFFF 2B0000-2BFFFF 2C0000-2CFFFF 2D0000-2DFFFF 2E0000-2EFFFF 2F0000-2FFFFF 300000-30FFFF 310000-31FFFF 320000-32FFFF 330000-33FFFF 340000-34FFFF 350000-35FFFF 360000-36FFFF 370000-37FFFF 380000-38FFFF 390000-39FFFF 3A0000-3AFFFF 3B0000-3BFFFF 3C0000-3CFFFF 3D0000-3DFFFF 3E0000-3EFFFF 3F0000-3F1FFF 3F2000-3F3FFF 3F4000-3F5FFF 3F6000-3F7FFF 3F8000-3F9FFF 3FA000-3FBFFF 3FC000-3FDFFF 3FE000-3FFFFF 130000-137FFF 138000-13FFFF 140000-147FFF 148000-14FFFF 150000-157FFF 158000-15FFFF 160000-167FFF 168000-16FFFF 170000-177FFF 178000-17FFFF 180000-187FFF 188000-18FFFF 190000-197FFF 198000-19FFFF 1A0000-1A7FFF 1A8000-1AFFFF 1B0000-1B7FFF 1B8000-1BFFFF 1C0000-1C7FFF 1C8000-1CFFFF 1D0000-1D7FFF 1D8000-1DFFFF 1E0000-1E7FFF 1E8000-1EFFFF 1F0000-1F7FFF 1F8000-1F8FFF 1F9000-1F9FFF 1FA000-1FAFFF 1FB000-1FBFFF 1FC000-1FCFFF 1FD000-1FDFFF 1FE000-1FEFFF 1FF000-1FFFFF
Note: The address bus is A20:A-1 in byte mode where BYTE# = VBIL or A20:A0 in word mode where BYTE# = VBIH
B B
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
6 (c)2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2007/07/17
EN29LV320A
Table 2B. Bottom Boot Sector Address Tables (EN29LV320AB)
U
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38
A20 - A12 000000000 000000001 000000010 000000011 000000100 000000101 000000110 000000111 000001xxx 000010xxx 000011xxx 000100xxx 000101xxx 000110xxx 000111xxx 001000xxx 001001xxx 001010xxx 001011xxx 001100xxx 001101xxx 001110xxx 001111xxx 010000xxx 010001xxx 010010xxx 010011xxx 010100xxx 010101xxx 010110xxx 010111xxx 011000xxx 011001xxx 011010xxx 011011xxx 011100xxx 011101xxx 011110xxx 011111xxx
Sector Size (Kbytes / Kwords) 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32
Address Range (h) Byte mode (x8) 000000-001FFF 002000-003FFF 004000-005FFF 006000-007FFF 008000-009FFF 00A000-00BFFF 00C000-00DFFF 00E000-00FFFF 010000-01FFFF 020000-02FFFF 030000-03FFFF 040000-04FFFF 050000-05FFFF 060000-06FFFF 070000-07FFFF 080000-08FFFF 090000-09FFFF 0A0000-0AFFFF 0B0000-0BFFFF 0C0000-0CFFFF 0D0000-0DFFFF 0E0000-0EFFFF 0F0000-0FFFFF 100000-10FFFF 110000-11FFFF 120000-12FFFF 130000-13FFFF 140000-14FFFF 150000-15FFFF 160000-16FFFF 170000-17FFFF 180000-18FFFF 190000-19FFFF 1A0000-1AFFFF 1B0000-1BFFFF 1C0000-1CFFFF 1D0000-1DFFFF 1E0000-1EFFFF 1F0000-1FFFFF
Address Range (h) Word Mode (x16) 000000-000FFF 001000-001FFF 002000-002FFF 003000-003FFF 004000-004FFF 005000-005FFF 006000-006FFF 007000-007FFF 008000-00FFFF 010000-017FFF 018000-01FFFF 020000-027FFF 028000-02FFFF 030000-037FFF 038000-03FFFF 040000-047FFF 048000-04FFFF 050000-057FFF 058000-05FFFF 060000-067FFF 068000-06FFFF 070000-077FFF 078000-07FFFF 080000-087FFF 088000-08FFFF 090000-097FFF 098000-09FFFF 0A0000-0A7FFF 0A8000-0AFFFF 0B0000-0B7FFF 0B8000-0BFFFF 0C0000-0C7FFF 0C8000-0CFFFF 0D0000-0D7FFF 0D8000-0DFFFF 0E0000-0E7FFF 0E8000-0EFFFF 0F0000-0F7FFF 0F8000-0FFFFF
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
7 (c)2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2007/07/17
EN29LV320A
SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 100000xxx 100001xxx 100010xxx 100011xxx 100100xxx 100101xxx 100110xxx 100111xxx 101000xxx 101001xxx 101010xxx 101011xxx 101100xxx 101101xxx 101110xxx 101111xxx 110000xxx 110001xxx 110010xxx 110011xxx 110100xxx 110101xxx 110110xxx 110111xxx 111000xxx 111001xxx 111010xxx 111011xxx 111100xxx 111101xxx 111110xxx 111111xxx 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 200000-20FFFF 210000-21FFFF 220000-22FFFF 230000-23FFFF 240000-24FFFF 250000-25FFFF 260000-26FFFF 270000-27FFFF 280000-28FFFF 290000-29FFFF 2A0000-2AFFFF 2B0000-2BFFFF 2C0000-2CFFFF 2D0000-2DFFFF 2E0000-2EFFFF 2F0000-2FFFFF 300000-30FFFF 310000-31FFFF 320000-32FFFF 330000-33FFFF 340000-34FFFF 350000-35FFFF 360000-36FFFF 370000-37FFFF 380000-38FFFF 390000-39FFFF 3A0000-3AFFFF 3B0000-3BFFFF 3C0000-3CFFFF 3D0000-3DFFFF 3E0000-3EFFFF 3F0000-3FFFFF 100000-107FFF 108000-10FFFF 110000-117FFF 118000-11FFFF 120000-127FFF 128000-12FFFF 130000-137FFF 138000-13FFFF 140000-147FFF 148000-14FFFF 150000-157FFF 158000-15FFFF 160000-167FFF 168000-16FFFF 170000-177FFF 178000-17FFFF 180000-187FFF 188000-18FFFF 190000-197FFF 198000-19FFFF 1A0000-1A7FFF 1A8000-1AFFFF 1B0000-1B7FFF 1B8000-1BFFFF 1C0000-1C7FFF 1C8000-1CFFFF 1D0000-1D7FFF 1D8000-1DFFFF 1E0000-1E7FFF 1E8000-1EFFFF 1F0000-1F7FFF 1F8000-1FFFFF
Note: The address bus is A20:A-1 in byte mode where BYTE# = VBIL or A20:A0 in word mode where BYTE# = VBIH
B B
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
8 (c)2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2007/07/17
EN29LV320A
PRODUCT SELECTOR GUIDE
Product Number Speed Option Max Access Time, ns (tBacc)
B
EN29LV320A -70 70 70 30 -90 90 90 35
Max CE# Access, ns (tBce)
B
Max OE# Access, ns (tBoe)
B
Notes: 1. Vcc=3.0 - 3.6 V for 70ns read operation
BLOCK DIAGRAM
Vcc Vss
RY/BY#
Block Protect Switches
DQ0-DQ15 (A-1)
Erase Voltage Generator State Control Program Voltage Generator Chip Enable Output Enable Logic
STB
Input/Output Buffers
WE#
Command Register CE# OE#
Data Latch
Y-Decoder Address Latch
STB
Y-Gating
Vcc Detector
Timer
X-Decoder
Cell Matrix
A0-A20
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
9 (c)2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2007/07/17
EN29LV320A
TABLE 3. OPERATING MODES 32M FLASH USER MODE TABLE
DQ8-DQ15 BYTE# BYTE# = VBIH = VBIL DBOUT DQ8DQ14= DBIN High-Z, DQ15 = DBIN A-1
B B B B B
Operation Read Write Accelerated Program CMOS Standby TTL Standby Output Disable Hardware Reset Sector (Group) Protect
CE# L L L VBcc 0.3V H L X
B
OE# L H H X X H X H
WE# H L L X X H X L
RESET # H H H VBcc 0.3V H H L
B
WP#/AC C L/H (Note 1) VBHH
A0A20 ABIN ABIN
B B
DQ0DQ7 DBOUT DBIN
B B
ABIN
B
DBIN
B
H H L/H L/H L/H
X X X X SA, A6=L, A1=H, A0=L SA, A6=H, A1=H, A0=L ABIN
B
High-Z High-Z High-Z High-Z (Note 2)
High-Z High-Z High-Z High-Z X
High-Z High-Z High-Z High-Z X
L
VBID
B
Sector Unprotect Temporary Sector Unprotect
B
L
H
L
VBID
B
(Note 1)
(Note 2)
X
X
X
X
X
VBID
B
(Note 1)
(Note 2)
(Note 2)
High-Z
L=logic low= VBIL, H=Logic High= VBIH, VBID =VBHH =11 0.5V = 10.5-11.5V, X=Don't Care (either L or H, but not floating ), SA=Sector Addresses, DBIN=Data In, DBOUT=Data Out, ABIN=Address In
B B B B B
Notes: 1. If WP#/ACC = VBIL , the two outermost boot sectors remain protected. If WP# / ACC = VBIH, the outermost boot sector protection depends on whether they were last protected or unprotected. If WP#/ACC = VBHH, all sectors will be unprotected.
B B B
2. Please refer to "Sector/Sector Group Protection & Chip Unprotection", Flowchart 7a and Flowchart 7b.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
10 (c)2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2007/07/17
EN29LV320A
TABLE 4. Autoselect Codes (Using High Voltage, VBID)
B
32M FLASH MANUFACTURER/DEVICE ID TABLE
A20 to A12 X A11 to A10 X A5 to A2 X DQ8 to DQ15 X 7Fh X X L L X X L L H H 22h X 22h X X L L H SA X VBID
B
Description
CE#
OE#
WE#
A9P
2
P
A8 HP
1
P
A7
A6
A1
A0
DQ7 to DQ0 1Ch
Manufacturer ID: Eon Device ID
(top boot sector)
L L L L L
L L L L L
H H H H H
VBID
B
X L
L
L
L
Word Byte Word Byte
X X
X X
VBID
B
X X
F6h F6h F9h F9h 01h
(Protected)
Device ID
(bottom boot sector)
VBID
B
Sector Protection Verification
X
X
L
X
H
L X
00h
(Unprotected)
L=logic low= VBIL, H=Logic High= VBIH, VBID =11 0.5V, X=Don't Care (either L or H, but not floating!), SA=Sector Addresses
B B B
Note: 1. A8=H is recommended for Manufacturing ID check. If a manufacturing ID is read with A8=L, the chip will output a configuration code 7Fh. 2. A9 = VBID is for HV A9 Autoselect mode only. A9 must be Vcc (CMOS logic level) for Command Autoselect Mode.
B
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
11 (c)2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2007/07/17
EN29LV320A USER MODE DEFINITIONS
Word / Byte Configuration
The signal set on the BYTE# pin controls whether the device data I/O pins DQ15-DQ0 operate in the byte or word configuration. When the BYTE# Pin is set at logic `1', then the device is in word configuration, DQ15-DQ0 are active and are controlled by CE# and OE#. On the other hand, if the BYTE# Pin is set at logic `0', then the device is in byte configuration, and only data I/O pins DQ0-DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8-DQ14 are tristated, and the DQ15 pin is used as an input for the LSB (A-1) address function.
Standby Mode
The EN29LV320A has a CMOS-compatible standby mode, which reduces the current to < 1A (typical). It is placed in CMOS-compatible standby when the CE# pin is at VBCC 0.5. RESET# and BYTE# pin must also be at CMOS input levels. The device also has a TTL-compatible standby mode, which reduces the maximum VBCC current to < 1mA. It is placed in TTL-compatible standby when the CE# pin is at VBIH. When in standby modes, the outputs are in a high-impedance state independent of the OE# input.
B B B B
Automatic Sleep Mode
The EN29LV320A has a automatic sleep mode, which minimizes power consumption. The devices will enter this mode automatically when the states of address bus remain stable for tacc + 30ns. ICC4 in the DC Characteristics table shows the current specification. With standard access times, the device will output new data when addresses change.
Read Mode
The device is automatically set to reading array data after device power-up or hardware reset. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm After the device accepts an Sector Erase Suspend command, the device enters the Sector Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Sector Erase Suspend mode, the system may once again read array data with the same exception. See "Sector Erase Suspend/Resume Commands" for more additional information. The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high or while in the autoselect mode. See the "Reset Command" for additional details.
Output Disable Mode
When the OE# pin is at a logic high level (VBIH), the output from the EN29LV320A is disabled. The output pins are placed in a high impedance state.
B
Autoselect Identification Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ15-DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VBID (10.5 V to 11.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes table. In addition, when verifying
B
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
12 (c)2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2007/07/17
EN29LV320A
sector protection, the sector address must appear on the appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The "Command Definitions" table shows the remaining address bits that are don't-care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ15-DQ0. To access the autoselect codes in-system; the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require VBID. See "Command Definitions" for details on using the autoselect mode.
B
Writing Command Sequences
To write a command or command sequence to program data to the device or erase data, the system has to drive WE# and CE# to VBIL, and OE# to VBIH.
B
For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. An erase operation can erase one sector or the whole chip. The system can also read the autoselect codes by entering the autoselect mode, which need the autoselect command sequence to be written. Please refer to the "Command Definitions" for all the available commands.
RESET#: Hardware Reset
When RESET# is driven low for tBRP, all output pins are tristates. All commands written in the internal state machine are reset to reading array data.
B
Please refer to timing diagram for RESET# pin in "AC Characteristics".
Sector/Sector Group Protection & Chip Unprotection
The hardware sector group protection feature disables both program and erase operations in any sector. The hardware chip unprotection feature re-enables both program and erase operations in previously protected sectors. A sector group implies three or four adjacent sectors that would be protected at the same time. Please see the following tables which show the organization of sector groups.
There are two methods to enable this hardware protection circuitry. The first one requires only that the RESET# pin be at VID and then standard microprocessor timings can be used to enable or disable this feature. See Flowchart 7a and 7b for the algorithm and Figure. 12 for the timings. When doing Chip Unprotect, all the unprotected sector groups must be protected prior to any unprotect write cycle. The second method is for programming equipment. This method requires VID to be applied to both OE# and A9 pins and non-standard microprocessor timings are used. This method is described in a separate document named EN29LV320A Supplement, which can be obtained by contacting a representative of Eon
Silicon Solution, Inc.
U
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
13 (c)2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2007/07/17
EN29LV320A
Top Boot Sector/Sector Group Organization Table (EN29LV320AT) for (Un)Protection
Sector Group
SG 0 SG 1 SG 2 SG 3 SG 4 SG 5 SG 6 SG 7 SG 8 SG 9 SG10 SG11 SG12 SG13 SG14 SG15 SG16 SG17 SG18 SG19 SG20 SG21 SG22 SG23
Sectors
SA 0-SA 3 SA 4-SA 7 SA 8-SA11 SA12-SA15 SA16-SA19 SA20-SA23 SA24-SA27 SA28-SA31 SA32-SA35 SA36-SA39 SA40-SA43 SA44-SA47 SA48-SA51 SA52-SA55 SA56-SA59 SA60-SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70
A20-A12
0000XXXXX 0001XXXXX 0010XXXXX 0011XXXXX 0100XXXXX 0101XXXXX 0110XXXXX 0111XXXXX 1000XXXXX 1001XXXXX 1010XXXXX 1011XXXXX 1100XXXXX 1101XXXXX 1110XXXXX 111100XXX 111101XXX 111110XXX 111111000 111111001 111111010 111111011 111111100 111111101 111111110 111111111
Sector Group Size
64 Kbytes x 4 64 Kbytes x 4 64 Kbytes x 4 64 Kbytes x 4 64 Kbytes x 4 64 Kbytes x 4 64 Kbytes x 4 64 Kbytes x 4 64 Kbytes x 4 64 Kbytes x 4 64 Kbytes x 4 64 Kbytes x 4 64 Kbytes x 4 64 Kbytes x 4 64 Kbytes x 4 64 Kbytes x 3 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes
Bottom Boot Sector/Sector Group Organization Table (EN29LV320AB) for (Un)Protection
Sector Group
SG23 SG22 SG21 SG20 SG19 SG18 SG17 SG16 SG15 SG14 SG13 SG12 SG11 SG10 SG 9 SG 8 SG SG SG SG SG SG SG SG 7 6 5 4 3 2 1 0
Sectors
SA70-SA67 SA66-SA63 SA62-SA59 SA58-SA55 SA54-SA51 SA50-SA47 SA46-SA43 SA42-SA39 SA38-SA35 SA34-SA31 SA30-SA27 SA26-SA23 SA22-SA19 SA18-SA15 SA14-SA11 SA10-SA 8 SA SA SA SA SA SA SA SA 7 6 5 4 3 2 1 0
A20-A12
1111XXXXX 1110XXXXX 1101XXXXX 1100XXXXX 1011XXXXX 1010XXXXX 1001XXXXX 1000XXXXX 0111XXXXX 0110XXXXX 0101XXXXX 0100XXXXX 0011XXXXX 0010XXXXX 0001XXXXX 000011XXX 000010XXX 000001XXX 000000111 000000110 000000101 000000100 000000011 000000010 000000001 000000000
Sector Group Size
64 Kbytes x 4 64 Kbytes x 4 64 Kbytes x 4 64 Kbytes x 4 64 Kbytes x 4 64 Kbytes x 4 64 Kbytes x 4 64 Kbytes x 4 64 Kbytes x 4 64 Kbytes x 4 64 Kbytes x 4 64 Kbytes x 4 64 Kbytes x 4 64 Kbytes x 4 64 Kbytes x 4 64 Kbytes x 3 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Rev. B, Issue Date: 2007/07/17
EN29LV320A
Write Protect / Accelerated Program (WP# / ACC)
The WP#/ACC pin provides two functions. The Write Protect (WP#) function provides a hardware method of protecting the outermost two 8K-byte Boot Sector. The ACC function allows faster manufacturing throughput at the factory, using an external high voltage. When WP#/ACC is Low, the device protects the outermost tw 8K-byte Boot Sector; no matter the sectors are protected or unprotected using the method described in "Sector/Sector Group Protection & Chip Unprotection", Program and Erase operations in these sectors are ignored. When WP#/ACC is High, the device reverts to the previous protection status of the outermost two 8K-byte boot sector. Program and Erase operations can now modify the data in the two outermost 8K-byte Boot Sector unless the sector is protected using Sector Protection. When WP#/ACC is raised to VHH the memory automatically enters the Unlock Bypass mode(please refer to "Command Definitions"), temporarily unprotects every protected sectors, and reduces the time required for program operation. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. When WP#/ACC returns to VIH or VIL, normal operation resumes. The transitions from VIH or VIL to VHH and from VHH to VIH or VIL must be slower than tBVHHB, see Figure 11. Note that the WP#/ACC pin must not be left floating or unconnected. In addition, WP#/ACC pin must not be at VHH for operations other than accelerated programming. It could cause the device to be damaged. Never raise this pin to VHH from any mode except Read mode, otherwise the memory may be left in an indeterminate state. A 0.1F capacitor should be connected between the WP#/ACC pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during Unlock Bypass Program.
Temporary Sector Unprotect
Start
This feature allows temporary unprotection of previously protected sector groups to change data while in-system. The Temporary Sector Unprotect mode is activated by setting the RESET# pin to VBIDB. During this mode, formerly protected sectors can be programmed or erased by simply selecting the sector addresses. Once VBIDB is removed from the RESET# pin, all the previously protected sectors are protected again. See accompanying flowchart and figure 10 for more timing details.
Notes: 1. All protected sectors are unprotected. (If WP#/ACC=VBIL, outermost boot sectors will remain protected.) 2. Previously protected sectors are protected again.
B
Reset#=VBID (note 1)
B B B
Perform Erase or Program Operations RESET#=VBIH
B
Temporary Sector Unprotect Completed (note 2)
B
COMMON FLASH INTERFACE (CFI)
The common flash interface (CFI) specification outlines device and host systems software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC IDindependent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Rev. B, Issue Date: 2007/07/17
EN29LV320A
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 5-8.In word mode, the upper address bits (A7-MSB) must be all zeros. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode and the system can read CFI data at the addresses given in Tables 5-8. The system must write the reset command to return the device to the autoselect mode.
Table 5. CFI Query Identification String
Addresses (Word Mode) 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Adresses (Byte Mode) 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h Description Query Unique ASCII string "QRY" Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists)
Table 6. System Interface String
Addresses (Word Mode) 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Addresses (Byte Mode) 36h 38h 3Ah 3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch Data 0027h 0036h 0000h 0000h 0004h 0000h 000Ah 0000h 0005h 0000h 0004h 0000h Description Vcc Min (write/erase) DQ7-DQ4: volt, DQ3 -DQ0: 100 millivolt Vcc Max (write/erase) DQ7-DQ4: volt, DQ3 -DQ0: 100 millivolt Vpp Min. voltage (00h = no Vpp pin present) Vpp Max. voltage (00h = no Vpp pin present) Typical timeout per single byte/word write 2PN S Typical timeout for Min, size buffer write 2PN S (00h = not supported) Typical timeout per individual block erase 2PN ms Typical timeout for full chip erase 2PN ms (00h = not supported) Max. timeout for byte/word write 2PN times typical Max. timeout for buffer write 2PN times typical Max. timeout per individual block erase 2PN times typical Max timeout for full chip erase 2PN times typical (00h = not supported)
P P P P P P P P
Table 7. Device Geometry Definition
Addresses (Word mode) 27h 28h 29h Addresses (Byte Mode) 4Eh 50h 52h Data 0016h 0002h 0000h Description Device Size = 2PN bytes
P
Flash Device Interface description (refer to CFI publication 100)
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This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Rev. B, Issue Date: 2007/07/17
EN29LV320A
2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 54h 56h 58h 5Ah 5Ch 5Eh 60h 62h 64h 66h 68h 6Ah 6Ch 6Eh 70h 72h 74h 76h 78h 0000h 0000h 0002h 0007h 0000h 0020h 0000h 003Eh 0000h 0000h 0001h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h Max. number of byte in multi-byte write = 2PN (00h = not supported) Number of Erase Block Regions within device
P
Erase Block Region 1 Information (refer to the CFI specification of CFI publication 100)
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
Table 8. Primary Vendor-specific Extended Query
Addresses (Word Mode) 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh Addresses (Byte Mode) 80h 82h 84h 86h 88h 8Ah 8Ch 8Eh 90h 92h 94h 96h 98h 9Ah 9Ch 9Eh Data 0050h 0052h 0049h 0031h 0031h 0000h 0002h 0004h 0001h 0004h 0000h 0000h 0000h 00A5h 00B5h 0002h/ 0003h Description Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock 0 = Required, 1 = Not Required Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 01 = 29F040 mode, 02 = 29F016 mode, 03 = 29F400 mode, 04 = 29LV800A mode Simultaneous Operation 00 = Not Supported, 01 = Supported Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page Minimum ACC (Acceleration) Supply Voltage 00 = Not Supported, DQ7-DQ4 : Volts, DQ3-DQ0 : 100mV Maximum ACC (Acceleration) Supply Voltage 00 = Not Supported, DQ7-DQ4 : Volts, DQ3-DQ0 : 100mV Top/Bottom Boot Sector Identifier 02h = Bottom Boot, 03h = Top Boot
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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EN29LV320A Hardware Data protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes as seen in the Command Definitions table. Additionally, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by false system level signals during Vcc power up and power down transitions, or from system noise.
Low VBCC Write Inhibit
B
When Vcc is less than VBLKO, the device does not accept any write cycles. This protects data during Vcc power up and power down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until Vcc is greater than VBLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when Vcc is greater than VBLKO.
B B B
Write Pulse "Glitch" protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VBIL, CE# = VBIH, or WE# = VBIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. If CE#, WE#, and OE# are all logical zero (not recommended usage), it will be considered a read.
B B B
Power-up Write Inhibit
During power-up, the device automatically resets to READ mode and locks out write cycles. Even with CE# = VBIL, WE#= VBIL and OE# = VBIH, the device will not accept commands on the rising edge of WE#.
B B B
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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EN29LV320A
COMMAND DEFINITIONS
The operations of the device are selected by one or more commands written into the command register. Commands are made up of data sequences written at specific addresses via the command register. The sequences for the specified operation are defined in the Command Definitions table (Table 9). Incorrect addresses, incorrect data values or improper sequences will reset the device to Read Mode.
Table 9. EN29LV320A Command Definitions
Bus Cycles Command Sequence Read Reset Manufacturer ID Device ID Top Boot Device ID Bottom Boot Sector Protect Verify Word 4 Byte Word Byte Word Byte Word 4 Byte Word Byte Word Unlock Bypass Byte 3 2 2 6 6 1 1 1 4 AAA 555 AAA 555 AAA XXX XXX 555 AAA 555 AAA xxx xxx 55 AA AA A0 90 AA AA B0 30 98 AA 4 AAA 555 AAA 555 AAA 555 AA 555 2AA 555 2AA 555 PA XXX 2AA 555 2AA 555 55 PD 00 55 55 555 AAA 555 AAA 80 80 555 AAA 555 AAA AA AA 2AA 555 2AA 555 55 55 555 AAA SA 10 30 55 AA
Cycles
1P Cycle
P
st
Addr
Data
Cycle Addr Data
P
2P
nd
3P Cycle
P
rd
4P Cycle
P
th
5P Cycle
P
th
6P Cycle
P
th
Addr
Data
Addr
Data
Addr
Data
Addr
Data
1 1
RA xxx 555
RD F0 2AA AA 555 2AA 555 2AA 555 2AA 55 AAA 555 AAA 555 AAA 20 A0 55 55 AAA 555 AAA 555 AAA 555 90 90 555 90 000 100 000 200 x01 x02 x01 x02 (SA) X02 (SA) X04 PA 7F 1C 7F 1C 22F6 F6 22F9 F9 00 01 00 01 PD
Autoselect
4
AA
55
90
Program
Unlock Bypass Program Unlock Bypass Reset Chip Erase Sector Erase Word Byte Word Byte
Sector Erase Suspend Sector Erase Resume CFI Query Word Byte
Address and Data values indicated are in hex. Unless specified, all bus cycles are write cycles RA = Read Address: address of the memory location to be read. This is a read cycle. RD = Read Data: data read from location RA during Read operation. This is a read cycle. PA = Program Address: address of the memory location to be programmed. X = Don't-Care PD = Program Data: data to be programmed at location PA SA = Sector Address: address of the Sector to be erased or verified. Address bits A20-A12 uniquely select any Sector.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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EN29LV320A
Reading Array Data
The device is automatically set to reading array data after power up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. Following a Sector Erase Suspend command, Sector Erase Suspend mode is entered. The system can read array data using the standard read timings from sectors other than the one which is being erase-suspended. If the system reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Sector Erase Suspend mode, the system may once again read array data with the same exception. The Reset command must be issued to re-enable the device for reading array data if DQ5 goes high during an active program or erase operation or while in the autoselect mode. See next section for details on Reset.
Reset Command
Writing the reset command to the device resets the device to reading array data. Address bits are don't-care for this command. The reset command may be written between the cycle sequences in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Sector Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the cycle sequences in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data. If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies in Sector Erase Suspend mode).
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and devices ID codes, and determine whether or not a sector (group) is protected. The Command Definitions table shows the address and data requirements. This is an alternative to the method that requires VBID on address bit A9 and is intended for commercial programmers.
B
Two unlock cycles followed by the autoselect command initiate the autoselect command sequence. Autoselect mode is then entered and the system may read at addresses shown in Table 9 any number of times, without needing another command sequence. The system must write the reset command to exit the autoselect mode and return to reading array data.
Word / Byte Programming Command
The device can be programmed by byte or by word, depending on the state of the BYTE# Pin. Programming the EN29LV320A is performed by using a four-bus-cycle operation (two unlock write cycles followed by the Program Setup command and Program Data Write cycle). When the program command is executed, no additional CPU controls or timings are necessary. An internal timer terminates the program operation automatically. Address is latched on the falling edge of CE# or WE#, whichever is last; data is latched on the rising edge of CE# or WE#, whichever is first.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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EN29LV320A
Any commands written to the device during the program operation are ignored. Programming status can be checked by sampling data on DQ7 (DATA# polling) or on DQ6 (toggle bit). When the program operation is successfully completed, the device returns to read mode and the user can read the data programmed to the device at that address. Note that data can not be programmed from a "0" to a "1". Attempting to do so may halt the operation and set DQ5 to "1", or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still "0". Only erase operations can convert a "0" to a "1". When programming time limit is exceeded, DQ5 will produce a logical "1" and a Reset command can return the device to Read mode. Programming is allowed in any sequence across sector boundaries.
Unlock Bypass
To speed up programming operation, the Unlock Bypass Command may be used. Once this feature is activated, the shorter two-cycle Unlock Bypass Program command can be used instead of the normal four-cycle Program Command to program the device. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset command can be accepted. This mode is exited after issuing the Unlock Bypass Reset Command. The device powers up with this feature disabled The device provides accelerated program operations through the WP#/ACC pin. When WP#/ACC is asserted to VBHH, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass Program command sequence.
B
Chip Erase Command
Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. The Command Definitions table shows the address and data requirements for the chip erase command sequence. Any commands written to the chip during the Embedded Chip Erase algorithm are ignored. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See "Write Operation Status" for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two un-lock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. The Command Definitions table shows the address and data requirements for the sector erase command sequence. Once the sector erase operation has begun, only the Sector Erase Suspend command is valid. All other commands are ignored. If there are several sectors to be erased, Sector Erase Command sequences must be issued for each sector. That is, only a sector address can be specified for each Sector Erase command. Users must issue another Sector Erase command for the next sector to be erased after the previous one is completed.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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When the Embedded Erase algorithm is completed, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. Refer to "Write Operation Status" for information on these status bits. Flowchart 4 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the "AC Characteristics" section for parameters, and to the Sector Erase Operations Timing diagram for timing waveforms.
Sector Erase Suspend / Resume Command
The Sector Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation. The Sector Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Addresses are don't-cares when writing the Sector Erase Suspend command. When the Sector Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. Normal read and write timings and command definitions apply. Please note that Autoselect command sequence can not be accepted during Sector Erase Suspend. Reading at any address within erase-suspended sectors produces status data on DQ7-DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See "Write Operation Status" for information on these status bits. After an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See "Write Operation Status" for more information. The Autoselect command is not supported during Sector Erase Suspend Mode. The system must write the Sector Erase Resume command (address bits are don't-care) to exit the sector erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Sector Erase Suspend command can be written after the device has resumed erasing.
WRITE OPERATION STATUS
DQ7: DATA# Polling
The EN29LV320A provides DATA# polling on DQ7 to indicate the status of the embedded operations. The DATA# Polling feature is active during the Word/Byte Programming, Sector Erase, Chip Erase, and Sector Erase Suspend. (See Table 10) When the embedded programming is in progress, an attempt to read the device will produce the complement of the data written to DQ7. Upon the completion of the programming operation, an attempt to read the device will produce the true data written to DQ7. DATA# polling is valid after the rising edge of the fourth WE# or CE# pulse in the four-cycle sequence for program. When the embedded Erase is in progress, an attempt to read the device will produce a "0" at the DQ7 output. Upon the completion of the embedded Erase, the device will produce the "1" at the DQ7 output during the read cycles. For Chip Erase or Sector Erase, DATA# polling is valid after the rising edge of the last WE# or CE# pulse in the six-cycle sequence.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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DATA# Polling must be performed at any address within a sector that is being programmed or erased and not a protected sector. Otherwise, DATA# polling may give an inaccurate result if the address used is in a protected sector. Just prior to the completion of the embedded operations, DQ7 may change asynchronously when the output enable (OE#) is low. This means that the device is driving status information on DQ7 at one instant of time and valid data at the next instant of time. Depending on the time the system samples the DQ7 output, it may read the status of valid data. Even if the device has completed the embedded operation and DQ7 has a valid data, the data output on DQ0-DQ6 may be still invalid. The valid data on DQ0-DQ7 should be read on the subsequent read attempts. The flowchart for DATA# Polling (DQ7) is shown on Flowchart 5. The DATA# Polling (DQ7) timing diagram is shown in Figure 6.
RY/BY#: Ready/Busy Status output
The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or completed. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to Vcc. In the output-low period, signifying Busy, the device is actively erasing or programming. This includes programming in the Erase Suspend mode. If the output is high, signifying the Ready, the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode.
DQ6: Toggle Bit I
The EN29LV320A provides a "Toggle Bit" on DQ6 to indicate the status of the embedded programming and erase operations. (See Table 10) During an embedded Program or Erase operation, successive attempts to read data from the device at any address (by active OE# or CE#) will result in DQ6 toggling between "zero" and "one". Once the embedded Program or Erase operation is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During Programming, the Toggle Bit is valid after the rising edge of the fourth WE# pulse in the four-cycle sequence. During Erase operation, the Toggle Bit is valid after the rising edge of the sixth WE# pulse for sector erase or chip erase. In embedded programming, if the sector being written to is protected, DQ6 will toggles for about 2 s, then stop toggling without the data in the sector having changed. In Sector Erase or Chip Erase, if all selected sectors are protected, DQ6 will toggle for about 100 s. The chip will then return to the read mode without changing data in all protected sectors. The flowchart for the Toggle Bit (DQ6) is shown in Flowchart 6. The Toggle Bit timing diagram is shown in Figure 7.
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a "1." This is a failure condition that indicates the program or erase cycle was not successfully completed. Since it is possible that DQ5 can become a 1 when the device has successfully completed its operation and has returned to read mode, the user must check again to see if the DQ6 is toggling after detecting a "1" on DQ5. The DQ5 failure condition may appear if the system tries to program a "1" to a location that is previously programmed to "0." Only an erase operation can change a "0" back to a "1." Under this condition, the device halts the operation, and when the operation has exceeded the timing limits,
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. (c)2004 Eon Silicon Solution, Inc., www.essi.com.tw
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DQ5 produces a "1." Under both these conditions, the system must issue the reset command to return the device to reading array data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the output on DQ3 can be checked to determine whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.) When sector erase starts, DQ3 switches from "0" to "1". This device does not support multiple sector erase (continuous sector erase) command sequences so it is not very meaningful since it immediately shows as a "1" after the first 30h command. Future devices may support this feature.
DQ2: Erase Toggle Bit II
The "Toggle Bit" on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erasesuspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to the following table to compare outputs for DQ2 and DQ6. Flowchart 6 shows the toggle bit algorithm, and the section "DQ2: Toggle Bit" explains the algorithm. See also the "DQ6: Toggle Bit I" subsection. Refer to the Toggle Bit Timings figure for the toggle bit timing diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Flowchart 6 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, after the initial two read cycles, the system determines that the toggle bit is still toggling. And the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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EN29LV320A
Write Operation Status
Operation Standard Mode Embedded Program Algorithm Embedded Erase Algorithm Reading within Erase Suspended Sector Reading within Non-Erase Suspended Sector Erase-Suspend Program DQ7 DQ7# 0 1 Data DQ7# DQ6 Toggle Toggle No Toggle Data Toggle DQ5 0 0 0 Data 0 DQ3 N/A 1 N/A Data N/A DQ2 No toggle Toggle Toggle Data N/A RY/BY# 0 0 1 1 0
Erase Suspend Mode
Table 10. Status Register Bits
DQ Name Logic Level `1' 7 Definition Erase Complete or erased sector in Sector Erase Suspend Erase On-Going Program Complete or data of non-erased sector during Sector Erase Suspend Program On-Going Erase or Program On-going Read during Sector Erase Suspend Erase Complete Program or Erase Error Program or Erase On-going Erase operation start Erase timeout period on-going Chip Erase, Sector Erase or Read within EraseSuspended sector. (When DQ5=1, Erase Error due to currently addressed Sector or Program on Erase-Suspended sector Read on addresses of non Erase-Suspend sectors
DATA#
POLLING
`0' DQ7 DQ7# `-1-0-1-0-1-0-1-'
6
TOGGLE BIT
DQ6 `-1-1-1-1-1-1-1-` `1' `0'
5
ERROR BIT SECTOR ERASE TIME BIT
3
`1' `0'
2
TOGGLE BIT
`-1-0-1-0-1-0-1-'
DQ2
Notes:
DQ7: DATA# Polling: indicates the P/E status check during Program or Erase, and on completion before checking bits DQ5 for Program or Erase Success. DQ6: Toggle Bit: remains at constant level when P/E operations are complete or erase suspend is acknowledged. Successive reads output complementary data on DQ6 while programming or Erase operation are on-going. DQ5: Error Bit: set to "1" if failure in programming or erase DQ3: Sector Erase Command Timeout Bit: Operation has started. Only possible command is Erase suspend (ES). DQ2: Toggle Bit: indicates the Erase status and allows identification of the erased Sector.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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(c)2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2007/07/17
EN29LV320A EMBEDDED ALGORITHMS
Flowchart 1. Embedded Program
START
Write Program Command Sequence (shown below)
Data# Poll Device
Verify Data?
Increment Address
No
Last Address? Yes Programming Done
Flowchart 2. Embedded Program Command Sequence
(See the Command Definitions section for more information.)
555H / AAH
2AAH / 55H
555H / A0H
PROGRAM ADDRESS / PROGRAM DATA
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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(c)2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2007/07/17
EN29LV320A
Flowchart 3. Embedded Erase
START
Write Erase Command Sequence
Data Poll from System or Toggle Bit successfully completed
Data =FFh? No Yes Erase Done
Flowchart 4. Embedded Erase Command Sequence
(See the Command Definitions section for more information.)
Chip Erase
Sector Erase
555H/AAH
555H/AAH
2AAH/55H
2AAH/55H
555H/80H
555H/80H
555H/AAH
555H/AAH
2AAH/55H
2AAH/55H
555H/10H
Sector Address/30H
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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(c)2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2007/07/17
EN29LV320A
Flowchart 5. DATA# Polling Algorithm
Start
Read Data
DQ7 = Data? No No DQ5 = 1? Yes Read Data (1)
Yes
Notes: (1) This second read is necessary in case the first read was done at the exact instant when the status data was in transition.
Yes DQ7 = Data? No Fail Pass
Start
Flowchart 6. Toggle Bit Algorithm
Read Data twice
No DQ6 = Toggle? Yes No DQ5 = 1? Yes Read Data twice (2)
Notes: (2) This second set of reads is necessary in case the first set of reads was done at the exact instant when the status data was in transition.
No DQ6 = Toggle? Yes Fail Pass
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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(c)2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2007/07/17
EN29LV320A
Flowchart 7a. In-System Sector (Group) Protect Flowchart
START PLSCNT = 1 RESET# = VID Wait 1 s
No Temporary Chip Unprotect Mode
First Write Cycle = 60h? Yes Set up sector (group) address
To Protect: Write 60h to sector addr with A6 = 0, A1 = 1, A0 = 0
Wait 150 s To Verify: Write 40h to sector(group) address with A6 = 0, A1 = 1, A0 = 0 Increment PLSCNT Wait 0.4 s Reset PLSCNT = 1
No No
Read from sector address with A6 = 0, A1 = 1, A0
PLSCNT = 25?
Data = 01h?
Yes
Yes
Device failed Protect another sector? No Remove VID from RESET# Write reset command Yes
Sector Protect Algorithm
Sector Protect complete
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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(c)2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2007/07/17
EN29LV320A
Flowchart 7b. In-System Chip Unprotect Flowchart
START
PLSCNT = 1 Protect all sectors (groups): The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address (see Diagram 7a.) RESET# = VID Wait 1 S
No First Write Cycle = 60h? Temporary Chip Unprotect Mode
Yes No All sectors protected?
Yes Set up first sector address Chip Unprotect: Write 60H to sector address with A6 = 1, A1 = 1, A0 = 0
Wait 15 ms
Increment PLSCNT
Verify Chip Unprotect: Write 40h to sector address with A6 = 1, A1 = 1, A0 =0
Wait 0.4 S
No
Read from sector address with A6 = 1, A1 = 1, A0 = 0
PLSCCNT = 1000? Yes Device failed
No
Data = 00h? Yes
Set up next sector (group) address
Last sector verified? Yes
No
Chip Unprotect Algorithm
Remove VID from RESET#
Write reset command
Chip Unprotect complete
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Rev. B, Issue Date: 2007/07/17
EN29LV320A
ABSOLUTE MAXIMUM RATINGS
Parameter Storage Temperature Plastic Packages Ambient Temperature With Power Applied Output Short Circuit CurrentP1
P
Value -65 to +125 -65 to +125 -55 to +125 200
P
Unit C C C MA V
A9, OE#, RESET# WP#/ACCP2
Pand P
-0.5 to +11.5
Voltage with Respect to Ground
All other pins 3
P P
-0.5 to Vcc+0.5
V
Vcc
-0.5 to + 4.0
V
Notes: 1. No more than one output shorted at a time. Duration of the short circuit should not be greater than one second. 2. Minimum DC input voltage on A9, OE#, RESET# and WP#/ACC pins is -0.5V. During voltage transitions, A9, OE#, RESET# and WP#/ACC pins may undershoot VBss to -1.0V for periods of up to 50ns and to -2.0V for periods of up to 20ns. See figure below. Maximum DC input voltage on A9, OE#, and RESET# is 11.5V which may overshoot to 12.5V for periods up to 20ns. 3. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, inputs may undershoot VBss to -1.0V for periods of up to 50ns and to -2.0 V for periods of up to 20ns. See figure below. Maximum DC voltage on output and I/O pins is VBcc + 0.5 V. During voltage transitions, outputs may overshoot to VBcc + 1.5 V for periods up to 20ns. See figure below. 4. Stresses above the values so mentioned above may cause permanent damage to the device. These values are for a stress rating only and do not imply that the device should be operated at conditions up to or above these values. Exposure of the device to the maximum rating values for extended periods of time may adversely affect the device reliability.
B B B B
RECOMMENDED OPERATING RANGESP1
P
Parameter Ambient Operating Temperature Commercial Devices Industrial Devices
Value 0 to 70 -40 to 85
Unit C
Operating Supply Voltage Vcc
1.
Full Voltage Range: 2.7 to 3.6V
V
Recommended Operating Ranges define those limits between which the functionality of the device is guaranteed.
Vcc +1.5V
Maximum Negative Overshoot Waveform
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Maximum Positive Overshoot Waveform 31
(c)2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2007/07/17
EN29LV320A
DC Characteristics Table 11. DC Characteristics
(TBa = 0C to 70C or - 40C to 85C; VBCC = 2.7-3.6V)
B B
Symbol IBLI
B
Parameter Input Leakage Current
Test Conditions 0V VBIN Vcc
B
Min
Typ
Max 5 5
Unit A A mA mA mA A A uA V V V V V V V
IBLO
B
Output Leakage Current Active Read Current ( Byte mode )
B
0V VBOUT Vcc
B
IBCC1 IBCC2
B
Active Read Current ( Word mode ) Supply Current (Program or Erase) Supply Current (Standby - CMOS)
B
CE# = VBIL ; OE# = VBIH ; f = 5MHZ
B B
9 9 20 1 1 1 -0.5 0.7 x Vcc 10.5 10.5
16 16 30 5.0 5.0 5.0 0.8 Vcc 0.3 11.5 11.5 0.45
CE# = VBIL, OE# = VBIH ,
B B
IBCC3 IBCC4
B
WE# = VBIL CE# = BYTE# = RESET# = Vcc 0.3V (Note 1)
B
Reset Current Automatic Sleep Mode
B
RESET# = Vss 0.3V VBIH = Vcc 0.3V
B
IBCC5 VBIL
B
VBIL = Vss 0.3V
B
Input Low Voltage
B
VBIH VBHH
B
Input High Voltage #WP/ACC Voltage (Write Protect / Program Acceleration) Voltage for Autoselect or Temporary Sector Unprotect Output Low Voltage Output High Voltage TTL
VBID
B
VBOL
B
IBOL = 4.0 mA
B
IBOH = -2.0 mA
B
VBOH
B
Output High Voltage CMOS VBLKO
B
IBOH = -100 A,
B
0.85 x Vcc Vcc 0.4V 2.3 2.5
Supply voltage (Erase and Program lock-out)
V
Notes:
1. BYTE# pin can also be GND 0.3V. BYTE# and RESET# pin input buffers are always enabled so that
they draw power if not at full CMOS supply voltages.
2. Maximum IBCC specifications are tested with Vcc = Vcc max.
B
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Rev. B, Issue Date: 2007/07/17
EN29LV320A
Test Conditions
3.3 V
2.7 k
Device under Test
CL
6.2 k
Note: Diodes are IN3064 or equivalent
Test Specifications
Test Conditions Output Load Output Load Capacitance, CBL
B
-70 30 5 0.0-3.0 1.5 1.5
-90 1 TTL Gate 100 5 0.0-3.0 1.5 1.5
Unit pF ns V V V
Input Rise and Fall times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels
Notes: 1. Vcc=3.0 - 3.6 V for 70ns read operation
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Rev. B, Issue Date: 2007/07/17
EN29LV320A
AC CHARACTERISTICS Hardware Reset (RESET#)
Parameter Std tREADY tREADY tRP tRH tRPD Description Reset# Pin Low to Read or Write Embedded Algorithms Reset# Pin Low to Read or Write Non Embedded Algorithms Reset# Pulse Width Reset# High Time Before Read Reset# to Standby Mode Test Setup Max Max Min Min Min Speed options -70 -90 20 500 500 50 20 Unit s nS nS nS s
Figure 1. AC Waveforms for RESET# Reset# Timings
RY/BY#
0V
CE# OE#
tRH
RESET#
tRP
tREADY
Reset Timings NOT During Automatic Algorithms
RY/BY#
tREADY
CE# OE#
RESET#
tRP tRH
Reset Timings During Automatic Algorithms
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Rev. B, Issue Date: 2007/07/17
EN29LV320A
AC CHARACTERISTICS Word / Byte Configuration (BYTE#)
Std Parameter tBBCS tBCBH tBRBH
B B B
Speed Description BYTE# to CE# switching setup time CE# to BYTE# switching hold time RY/BY# to BYTE# switching hold time Min Min Min -70 0 0 0 -90 0 0 0
Unit ns ns ns
Figure 2. AC Waveforms for BYTE#
CE#
OE#
Byte# tBCS tCBH
Byte# timings for Read Operations
CE#
WE#
Byte# tRBH
tBCS RY/BY#
Byte #timings for Write Operations
Note: Switching BYTE# pin not allowed during embedded operations
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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(c)2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2007/07/17
EN29LV320A
AC CHARACTERISTICS Table 12. Read-only Operations Characteristics
Parameter Symbols JEDEC Standard Description Read Cycle Time
B
Test Setup Min CE# = VBIL OE#B = VIL
B B B B B
Speed Options -70 70 70 70 30 20 20 0 0 10 -90 90 90 90 35 20 20 0 0 10 Unit ns ns ns ns ns ns ns ns ns
tBAVAV
B
tBRC
B B
tBAVQV tBELQV
B
tBACC tBCE
B
Address to Output Delay Chip Enable To Output Delay
Max Max Max Max Max Min Min Min
OE#B = VBIL
B B
tBGLQV
B
tBOE
B
Output Enable to Output Delay Chip Enable to Output High Z Output Enable to Output High Z Output Hold Time from Addresses, CE# or OE#, whichever occurs first
B
tBEHQZ
B
tBDF
B B
tBGHQZ tBAXQX
B
tBDF
B
tBOH
tBOEH
B
Output Enable Hold Time
Read Toggle and Data# Polling
Notes: For - 70
Vcc = 3.0V - 3.6V Output Load: 1 TTL gate and 30pF Input Rise and Fall Times: 5ns Input Pulse Levels: 0.0 V to 3.0 V Timing Measurement Reference Level, Input and Output: 1.5 V Vcc = 2.7V - 3.6V Output Load: 1 TTL gate and 100 pF Input Rise and Fall Times: 5 ns Input Pulse Levels: 0.0 V to 3.0 V Timing Measurement Reference Level, Input and Output: 1.5 V
- 90
Figure 3. AC Waveforms for READ Operations
tBRC
B
Addresses
Addresses Stable
tBACC
CE#
tBDF tBOE
B
OE#
tBOEH
B
WE#
tBCE
B
tBOH
Output Valid
Outputs
HIGH Z
RESET#
RY/BY#
0V
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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(c)2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2007/07/17
EN29LV320A
AC CHARACTERISTICS Table 13. Write (Erase/Program) Operations
Parameter Symbols JEDEC Standard Description Write Cycle Time
B
Speed Options -70 Min Min Min Min Min Min MIn Min Min Min Min Min Min Typ Typ 70 0 45 30 0 0 0 10 0 0 0 45 20 8 8 -90 90 0 45 45 0 0 0 10 0 0 0 45 20 8 s Word 8 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
tBAVAV
B
tBWC
B
tBAVWL tBWLAX
B
tBAS
B
Address Setup Time
B
tBAH
B
Address Hold Time Data Setup Time
B
tBDVWH tBWHDX
B
tBDS
B
tBDH tBOES
B
Data Hold Time Output Enable Setup Time Output Read Enable Toggle and Hold Time DATA# Polling Read Recovery Time before Write (OE# High to WE# Low)
B
tBOEH
B
tBGHWL
B
tBGHWL tBCS
B
tBELWL
B
CE# Setup Time
B
tBWHEH
B
tBCH
B
CE# Hold Time
B
tBWLWH tBWHDL
B
tBWP
Write Pulse Width
B
tBWPH
Write Pulse Width High Programming Operation
B
Byte
tBWHW1
B
tBWHWH1
tBWHW1
B
tBWHWH1
B
Accelerated Programming Operation (Word AND Byte Mode)
Typ
7
7
s
tBWHW2
B
tBWHWH2
B
Sector Erase Operation
Typ
0.5
0.5
s
tBWHW3
B
tBWHWH3
B
Chip Erase Operation Vcc Setup Time
Typ Min
70 50
70 50
s s
tBVCS
B
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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(c)2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2007/07/17
EN29LV320A
AC CHARACTERISTICS Table 14. Write (Erase/Program) Operations
Alternate CE# Controlled Writes Parameter Symbols JEDEC Standard Description Write Cycle Time
B
Speed Options -70 Min Min Min Min Min Min Min Min Min Min Min Byte Word Typ Typ 70 0 45 30 0 0 0 0 0 35 20 8 8 -90 90 0 45 45 0 0 0 0 0 45 20 8 s 8 Unit ns ns ns ns ns ns ns ns ns ns ns
tBAVAV
B
tBWC tBAS
B
tBAVEL
B
Address Setup Time
B
tBELAX
B
tBAH
B
Address Hold Time Data Setup Time
B
tBDVEH tBEHDX
B
tBDS
B
tBDH tBOES
B
Data Hold Time Output Enable Setup Time
B
tBGHEL
B
tBGHEL
B
Read Recovery Time before Write (OE# High to CE# Low) WE# Setup Time
tBWLEL tBELEH
B
tBWS
B B
tBEHWH tBEHEL
B
tBWH
B
WE# Hold Time CE# Pulse Width
B
tBCP
B
tBCPH
B
CE# Pulse Width High Programming Operation
B
tBWHW1
tBWHWH1
tBWHW1
B
tBWHWH1
B
Accelerated Programming Operation (Word AND Byte Mode)
Typ
7
7
s
tBWHW2
B
tBWHWH2
B
Sector Erase Operation
Typ
0.5
0.5
s
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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(c)2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2007/07/17
EN29LV320A
AC CHARACTERISTICS Figure 4. AC Waveforms for Chip/Sector Erase Operations Timings
Erase Command Sequence (last 2 cycles) Read Status Data (last two cycles)
tWC Addresses 0x2AA
tAS SA
tAH VA
0x555 for chip erase
VA
CE# tGHWL OE# tWP WE# tCS tWPH tCH
tWHWH2 or tWHWH3 Data 0x55 tDS 0x30 Status DOUT
tDH
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes: 1. SA=Sector Address (for sector erase), VA=Valid Address for reading status, DBout =true data at read address. 2. VBcc shown only to illustrate tBvcs measurement references. It cannot occur as shown during a valid command sequence.
B B B
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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(c)2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2007/07/17
EN29LV320A
Figure 5. Program Operation Timings
Program Command Sequence (last 2 cycles) Program Command Sequence (last 2 cycles)
tWC Addresses 0x555
tAS PA
tAH PA PA
CE# tGHWL OE# tWP tCH
WE# tCS Data tDS
OxA0
tWPH tWHWH1 PD Status DOUT tRB
tDH RY/BY# tVCS
tBUSY
VCC
Notes: 1. PA=Program Address, PD=Program Data, DBOUT is the true data at the program address. 2. VBCC shown in order to illustrate tBVCS measurement references. It cannot occur as shown during a valid command sequence.
B B B
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Rev. B, Issue Date: 2007/07/17
EN29LV320A
Figure 6. AC Waveforms for /DATA Polling During Embedded Algorithm Operations
tRC Addresses tCH CE#
VA VA VA
tACC tCE
tOE OE# tOEH
tDF
WE#
tOH
DQ[7]
Complement
Complement
True
Valid Data
DQ[6:0] tBUS RY/BY#
Notes:
Status Data
Status Data
True
Valid Data
1. VA=Valid Address for reading Data# Polling status data 2. This diagram shows the first status cycle after the command sequence, the last status read cycle and the array data read cycle.
Figure 7. AC Waveforms for Toggle Bit During Embedded Algorithm Operations
tRC Addresses tCH CE# VA tACC tCE VA VA VA
tOE OE# tOEH
tDF
WE#
tOH
DQ6, DQ2 tBUSY RY/BY#
Valid Status (first read)
Valid Status (second d)
Valid Status (stops toggling)
Valid Data
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Rev. B, Issue Date: 2007/07/17
EN29LV320A
Figure 8. Alternate CE# Controlled Write Operation Timings
0x555 for Program 0x2AA for Erase PA for Program SA for Sector Erase 0x555 for Chip Erase
Addresses tWC WE# tGHEL OE# tWS CE# tDS Data
0xA0 for Program
PD for Program 0x30 for Sector Erase 0x10 for Chip Erase
VA
tAS
tAH
tWH
tCP
tCPH
tCWHWH1 / tCWHWH2 / tCWHWH3
tDH
tBUSY Status DOUT
RY/BY# tRH Reset#
Notes: PA = address of the memory location to be programmed. PD = data to be programmed at byte address. VA = Valid Address for reading program or erase status DBout = array data read at VA Shown above are the last two cycles of the program or erase command sequence and the last status read cycle RESETt# shown to illustrate tBRH measurement references. It cannot occur as shown during a valid command sequence.
B B
Figure 9. DQ2 vs. DQ6
Enter Embedded Erase Erase Suspend Enter Erase Suspend Program Enter Suspend Read Enter Suspend Program Erase Resume
WE#
Erase
Erase Suspend Read
Erase
Erase Complete
DQ6
DQ2
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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(c)2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2007/07/17
EN29LV320A
AC CHARACTERISTICS Temporary Sector Unprotect
Parameter Std tBVIDR
B B
Description VBID Rise and Fall Time Min Min Min
Speed Option -70 -90 500 500 4
Unit Ns Ns
s
tBVIHH
B
tBRSP
B
VBHH Rise and Fall Time RESET# Setup Time for Temporary Sector Unprotect
B
Figure 10. Temporary Sector Unprotect Timing Diagram
VID
RESET#
0 or 3 V
0 or 3 V tVIDR tVIDR
CE#
WE# tRSP
RY/BY#
AC CHARACTERISTICS Write Protect / Accelerated Program Figure 11. Accelerated Program Timing Diagram
VBHH
B
WP#/ACC
0 or 3 V
0 or 3 V tBVHH
B
tBVHH
B
CE#
WE# tBRSP
B
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Rev. B, Issue Date: 2007/07/17
EN29LV320A
AC CHARACTERISTICS Sector (Group) Protect and Chip Unprotect Figure 12. Sector (Group) Protect and Chip Unprotect Timing Diagram
VID
Vcc
RESET#
0V 0V
tVIDR
tVIDR
SA, A6,A1,A0 Data 60h
Valid 60h
Valid 40h Verify >0.4S
Valid Status
Sector Protect/Unprotect CE# WE# >1S OE# Notes:
Protect: 150 uS Unprotect: 15 mS
Use standard microprocessor timings for this device for read and write cycles. For Sector (Group) Protect, use A6=0, A1=1, A0=0. For Chip Unprotect, use A6=1, A1=1, A0=0.
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Rev. B, Issue Date: 2007/07/17
EN29LV320A
ERASE AND PROGRAM PERFORMANCE
Parameter Sector Erase Time Chip Erase Time Byte Programming Time Accelerated Byte/Word Program Time Word Programming Time Chip Programming Time Byte Word Erase/Program Endurance Typ 0.5 70 8 7 8 35 17 100K 300 200 300 100 50 Cycles Minimum 100K cycles Limits Max 10 Unit Sec Sec S S S Sec Excludes system level overhead Comments Excludes 00h programming prior to erasure
Note: Typical Conditions are room temperature, 3V and checkboard pattern programmed.
LATCH UP CHARACTERISTICS
Parameter Description Input voltage with respect to VBss on all pins except I/O pins (including A9, Reset and OE#)
B
Min -1.0 V -1.0 V -100 mA
Max 12.0 V Vcc + 1.0 V 100 mA
Input voltage with respect to VBss on all I/O Pins
B
Vcc Current
Note: These are latch up characteristics and the device should never be put under these conditions. Refer to Absolute Maximum ratings for the actual operating limits.
48-PIN TSOP PACKAGE CAPACITANCE
Parameter Symbol CBIN
B
Parameter Description Input Capacitance
Test Setup VBIN = 0
B
Typ 6 8.5 7.5
Max 7.5 12 9
Unit pF pF pF
CBOUT
B
Output Capacitance Control Pin Capacitance
VBOUT = 0
B
CBIN2
B
VBIN = 0
B
Note: Test conditions are Temperature = 25C and f = 1.0 MHz.
DATA RETENTION
Parameter Description Minimum Pattern Data Retention Time 125C 20 Years Test Conditions 150C Min 10 Unit Years
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Rev. B, Issue Date: 2007/07/17
EN29LV320A
FIGURE 13. TSOP 12mm x 20mm
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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EN29LV320A
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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EN29LV320A
FIGURE 14. 48TFBGA package outline
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
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Rev. B, Issue Date: 2007/07/17
EN29LV320A
Revisions List
Revision No A B Description Initial Release Date 2006/11/06
To correct the Table 11. DC Characteristics, IBCC4 (Reset 2007/07/17 Current) Unit from mA to A in page 32
This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
49
(c)2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2007/07/17

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